The present invention relates to a semiconductor integrated circuit and more specifically it relates to a semiconductor integrated circuit that performs digital/analog D/A conversion.
Current cell circuits that achieve output currents that are equal or exponentials of 2, are employed in a digital/analog converter (hereafter referred to as a D/A converter) and the like. An example of a D/A converter employing equal current cell circuits in the prior art is explained below with reference to FIG. 7.
As illustrated in FIG. 7, a D/A converter 400 comprises equal current cell circuits 450 arrayed in a matrix, a row decoder 410 and a first latch circuit 430 that make selections in the direction of the rows of the matrix of the equal current cell circuits 450, a column decoder 420 and a second latch circuit 440 that make selections in the direction of the columns of the matrix of the equal current cell circuits 450.
As shown in FIG. 7, the three high order bits of an input A (5:0), i.e., A5, A4 and A3, are input to the row decoder 410, and seven-bit data (the individual bits are indicated with reference numbers D0-D6) are output to the first latch circuit 430. In the row decoder 410, specific logic elements are provided in correspondence to the individual sets of data D0-D6 so that the truth table illustrated in FIG. 9 is achieved. In addition, the three low order bits of the input A (5:0), i.e., A2, A1 and A0 are input to the column decoder 420, and seven-bit data are output to the second latch circuit 440 in a similar manner.
Now, the structure of the row decoder 410 and its relationship with its output, i.e. , the individual sets of data D0-D6, are explained. Since the structure of the column decoder 420 is essentially identical to that of the row decoder 410, its explanation is omitted.
The data D0 are the output of a three-input NAND element NAND0 into which inverted signals of A5, A4 and A3 are input. The data D1 are the output of a two-input NAND element NAND1 into which inverted signals of A5 and A4 are input. The data D2 are the output of a two-input NAND element NAND2 into which the output of a two-input OR element OR2 into which inverted signals of A4 and A3 are input and an inverted signal of A5 are input. The data D3 are the output of an inverter element INV5 into which an inverted signal of A5 is input. The data D4 are the output of a two-input NOR element NOR4 into which the output of a two-input AND element AND4 into which inverted signals of A4 an A3 are input and an inverted signal of A5 are input. The data D5 are the output of a two-input NOR element NOR5 into which inverted signals of A5 and A4 are input. The data D6 are the output of a three-input NOR element NOR6 into which inverted signals of A5, A4 and A3 are input. The row decoder 410 structured as described above achieves the truth Table shown in FIG. 9.
The first latch circuit 430 latches the output of the row decoder 410 in synchronization with a clock CLK. The output of the first latch circuit 430 is input to the equal current cells 450, to be detailed later, as inputs i and i+1. Likewise, the second latch circuit 440 latches the output from the column decoder 420 in synchronization with the clock CLK. The output of the second latch circuit 440 is input to the equal current cells 450, to be detailed later, as an input j.
The equal current cells 450, which are provided in an 8xc3x978 matrix as illustrated in FIG. 7, are connected to the first latch circuit 430 and the second latch circuit 440. The inputs i and i+1 connected to the first latch circuit 430 and the input j connected to the second latch circuit 440 are input to the equal current cells 450.
An output Qm (m represents an integer equal to or greater than 0 and equal to or less than 6) of the first latch circuit 430 is input to the individual equal current cells in row m+2 as the input i and also is input to the individual equal current cells in row m+l as the input i +1. The input i in the first row that is not connected to the first latch circuit 430 is instead connected to a source Vdd, and likewise, the input i+1 in the eighth row that is not connected to the first latch circuit 430 is instead connected to the ground GND.
An output Qn (n represents an integer equal to or greater than 0 and equal to or less than 6) of the second latch circuit 440 is input to the individual equal current cells in row n as the input j. The input j in the seventh row that is not connected to the second latch circuit 440 is instead connected to the ground GND.
Now, the circuit structure of the equal current cells 450 is explained in reference to FIG. 8. The input i is input to one input of a NAND element 452 via inverter elements 456 and 457. The output of the inverter element 456 is connected to the gate terminal of an NMOS capacitor N1. The input i+1 and the input j are input to a two-input OR element 451. The output of the two-input OR element 451 is input to another input of the NAND element 452. The output of the NAND element 452 is connected to the gate terminal of an NMOS capacitor N2 and is also input to a current switch portion 459 which is to be detailed later.
Next, the structure of the current switch portion 459 in each equal current cell 450 is explained. A PMOS Q3, which is set in a drain saturation region by a bias voltage, functions as a constant current source. PMOS""s Q1 and Q2 constituting the current switch portion 459 are turned ON/OFF by a selection signal SEL which is an output from the two-input NAND element 452. The selection signal SEL is connected to the gate terminal of the PMOS Q1 via an inverter element 455 and an inverter element 454, and is also connected to the gate terminal of the PMOS Q2 via the inverter element 455.
When the selection signal SEL is 0, the PMOS Q1 is set to ON and the PMOS Q2 is set to OFF, whereas when the selection signal SEL is at 1, the PMOS Q1 is set to OFF and the PMOS Q2 is set to ON. In addition, when the selection signal SEL shifts either from 0 to 1 or from 1 to 0, the PMOS""s Q1 and Q2 are set to OFF or ON together. When the PMOS""s Q1 and Q2 are set to ON or OFF together, the drain voltage at the PMOS Q3 fluctuates to result in a fluctuation in the current in the output out due to charging/discharging of the incidental capacitance Cp to generate noise, which, in turn, affects the length of time required for settling.
When the PMOS Q1 is set to ON, the source Vdd is output as the output out via the PMOS Q1. When the PMOS Q2 is set to ON, on the other hand, the source Vdd is output as an output out b via the PMOS Q2. Both the outputs out and out b are wired throughout the matrix.
As an example, the operation of the equal current cells 450 that is performed when xe2x80x9c011010xe2x80x9d is input to the input A (5:0). The input A (5:0) is divided into 3-bit groups to be respectively input to the row decoder 410 and the column decoder 420. The row decoder 410 and the column decoder 420 have the same logic and achieve the truth table shown in FIG. 9. When xe2x80x9c011xe2x80x9d representing the high order three bits of the input is input to the row decoder 410, it outputs xe2x80x9c1110000xe2x80x9d as indicated in the truth table in FIG. 9. Likewise, when xe2x80x9c010xe2x80x9d representing the low order bits of the input is input to the column decoder 420, it outputs xe2x80x9c1100000xe2x80x9d as indicated in the truth table in FIG. 9.
The first latch circuit 430 and the second latch circuit 440 output their inputs in synchronization with the clock CLK. In the first row in the matrix of the equal current cells 450, since the inputs i and i+1 of the equal current cells 450 are at high level, the current is switched toward the out. The same applies to the second row and the third row.
Since the i input is at high level and the i+1 input is at low level in the fourth row, the output in the fourth row is determined by the j input. With the output of the second latch circuit 440 being xe2x80x9c1100000xe2x80x9d, the j input is set to 1 in the first column and the second column resulting in the current being switched toward the out. The current is switched toward the out b in the third column and subsequent columns in the fourth row.
Since the i input is set to low level in the fifth and subsequent rows, the current is switched toward the out b. As a result, the current corresponding to the 24 cells in the first through third rows and the current corresponding to the two cells in the first column and the second column in the fourth row flows toward the out. In other words, the current corresponding to 011010 (binary number)=26 flows toward the out.
Now, there is a problem with the D/A converter 400 in that, since the switch timing for the equal current cell is adjusted by employing the NMOS capacitors N1 and N2 to prevent glitches, power consumption increases as the load capacity increases.
In addition, it is difficult to match the timing for the inputs i and i+1 and the input j, and thus, due to inconsistency and the like occurring during production, glitches cannot be completely eliminated. This, in turn, results in problems such as degradation of the S/N (signal-to-noise) ratio and a great length of time required for settling.
An object of the present invention, which has been completed by addressing the problems of the semiconductor integrated circuit in the prior art discussed above, is to provide a new and improved semiconductor integrated circuit with which a reduction in the power consumption is achieved.
Another object of the present invention is to provide a new and improved semiconductor integrated circuit with which the S/N ratio can be improved.
In order to achieve the objects described above, a semiconductor integrated circuit comprising an equal current cell matrix achieved by arranging, in a matrix, equal current cells each having a current switch portion provided with a current source; a first decoder circuit that selects in the direction of the rows in the equal current cell matrix, a specific number of equal current cells; and a second decoder circuit that selects, in the direction of the columns in the equal current cell matrix, a specific number of equal current cells, wherein the equal current cells are each provided with a storage circuit that outputs a specific output signal to the current switch portion by synchronizing an output signal from the first decoder and an output signal from the second decoder, is provided.
Through this structure, since the storage circuit is provided in each equal current cell to switch the current, glitches can be completely eliminated from the signal output to the current switch portion by taking into consideration the delays at the first decoder and the second decoder and the timing of the clock to achieve an advantage of an improved S/N ratio. Furthermore, since no NMOS capacitance is required, the power consumption can be reduced.
Alternatively, the storage circuit may include a latch circuit that outputs a signal in synchronism with a clock signal. This structure will reduce the number of gates in comparison to a structure in which a flip-flop is employed to constitute the storage circuit to thereby further reduce the chip area.
As an alternative, the equal current cell circuits may each include a waveform shaping circuit for shaping the potential waveform of the output signal from the storage circuit at a rear stage relative to the storage circuit. By adopting this structure, if, for instance, transistors are provided at the current switch portion, the potential at which the output waveforms cross can be set to ensure that current flows through the transistors constituting the current switch portion by using the waveform shaping circuit and, therefore, an improvement in the S/N ratio can be achieved.
Furthermore, the waveform shaping circuit may include an S-R latch circuit including two-input NOR elements. In this structure, since the inverter and the S-R latch circuit are employed to ensure that one of the outputs of the waveform shaping circuit falls before the other output rises, the potential at which the output waveforms cross can be set at almost equal levels at the rise and the fall of the input waveform and as a result, since the crossing potential can be set simply by adjusting the delay times at the individual gates, design is facilitated in addition to the advantages described above.
It is even more desirable to provide a plurality of inverter elements having different threshold voltage values at the waveform shaping circuit. By adopting this structure, since the potential at which the output waveforms cross can be set by one inverter and two inverters to ensure that current flows to the PMOS constituting the current switch portion, an advantage is achieved in that an improvement in the S/N ratio is realized as in the second embodiment. In addition, being constituted with, for instance, three inverters, the number of gates can be reduced to achieve a reduction in chip area.